why PCIe TLP header has "Last DW BE" and "First DW BE"?

I've met a problem related to PCIe. I use a driver to write 0x12345678 to BAR0+offset, and use xilinx chipscope to see the waveform. On our Intel Rangeley board, we see TLP payload is split into two DWs, that is 00_00_00_78 56_34_12_00, while on a dell PC, we see only one DW in payload. I'm sure both case conform the PCIe specification. But I really wonder, why should PCIe specification has this kind of design, that is "Last DW BE" and "First DW BE" in 2nd DW of TLP header? Hope someone could help, thanks in advance.